A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system. FIG. 1 shows a typical computer system (10) having a microprocessor (12), memory (14), integrated circuits (16) that have various functionalities, and communication paths (18, 20), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system (10).
A clock signal is critical to the operation of a microprocessor-based computer system. The clock signal initiates and synchronizes the operation of almost all of the components of the typical computer system. As computers operate at increasing clock speeds, it becomes critical to ensure that clock signals on a microprocessor are provided to various logic elements on the microprocessor in an accurate and timely manner. However, due to one or more types of variations in fabrication, temperature, and voltage, clock signals may not arrive at various logic elements as expected.
Two components used within the computer system (10) to ensure clock signals arrive in an accurate and timely manner are a phase locked loop, or “PLL,” and a delay locked loop, or “DLL.” Both PLL and DLL circuits remove clock distribution delay. The PLL is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a system signal. The DLL is an electronic circuit that generates a copy of the clock signal at a fixed phase shift from the original clock signal.
The performance of PLL and DLL circuits are measured by characteristics of the clock signals, e.g., jitter, noise, and duty cycle. Duty cycle is the relationship between the high state time (high time) and low state time (low time). For example, if the high time of the signal is three quarters of each cycle, the duty cycle of the high time is 75%. If the high time of the signal is half of each cycle, the duty cycle of the high time is 50%. Commonly, components dependent upon output signals and input signals, particularly clock signals, require a 50% duty cycle. However, due to the variations mentioned above, the high times of a signal and the low times of the signal may not always be equal.
An approach designers have used to achieve a 50% duty cycle is the use of a frequency divider. The frequency divider may be integrated in the PLL or DLL design, or in other implementations, may precede or follow PLL and DLL circuits. FIG. 2 shows a typical frequency divider. The frequency divider (30) includes an inverter (32) and a positive edge triggered flip-flop (34). The inverter (32) inputs an output clock signal (clk 2). The flip-flop (34) inputs the inverted output clock signal to an input data terminal (D) of the flip-flop (34) and an input clock signal (clk 1) to a clock terminal (CLK) of the flip-flop (34).
An output terminal (Q) maintains the present state until the clock terminal (CLK) is triggered. The output terminal (Q) of the flip-flop (34) transitions from the previous state when the clock terminal (CLK) is triggered (i.e., transitions to high). For example, if the output terminal (Q) is low and the input data terminal (D) is high and the clock terminal (CLK) transitions to high, the output terminal (Q) transitions to high. When the clock terminal (CLK) transitions to low, the output terminal (Q) maintains the high state and the input data terminal (D) maintains the low state. The output terminal (Q) transitions to low when the clock terminal (CLK) transitions to high again.
FIG. 3 shows a timing diagram of the typical frequency divider shown in FIG. 2. FIG. 3 illustrates two defining characteristics of the frequency divider (30). First, the frequency divider (30) produces the output clock signal (clk 2) with a 50% duty cycle, even if the input clock signal (clk 1) doesn't have a 50% duty cycle. Second, a frequency of the output clock signal (clk 2) is half of the frequency of the input clock signal (clk 1). Further, the output clock signal (clk 2) is substantially delayed relative to the input clock signal (clk 1). The output clock signal (clk 2) transitions (high to low or low to high) for every rising edge of the input clock signal (clk 1). In this manner, the 50% duty cycle of the output clock signal (clk2) and halved frequency of the output clock signal (clk 2) (with respect to input clock signal (clk 1)) are generated. The frequency divider (30) cannot generate a duty cycle other than the 50% duty cycle.